This invention relates to an apparatus ensuring the accurate placement of semiconductor wafers onto respective platforms (or susceptors) within reaction chambers which are precisely (and adjustably) spaced apart, the apparatus providing compensation for dimensional variations due to mechanical tolerances and reducing the effects of thermal expansion or contraction with changes in temperature.
Today""s semiconductor circuits have features such as vias with diameters that are a small fraction of a micron, for example, only about 0.13 micron, with depths of 4 to 5 times the diameter. Such small via diameters and large depth to diameter ratios make it difficult with currently used materials (e.g., aluminum or copper) to properly metalize the vias completely down to their lower ends. Accordingly, a chemical vapor metalizing process using a highly volatile precursor compound of tungsten, such as tungsten hexaflouride (WF6), is advantageously used to metalize the vias. In order to keep the tungsten being deposited on the exposed surface of the wafer from being deposited beyond and/or beneath the edge or rim of the wafer, inert gas, such as argon or argon mixed with helium, is flowed in an annular stream of the gas upward and over the rim. Flowing such a stream of inert gas, termed xe2x80x9cedge-purgingxe2x80x9d, reduces or eliminates tungsten deposition adjacent the edge of the wafer by diluting or physically excluding the WF6 precursor gas. For edge-purging to be fully effective, however, each wafer should be accurately centered on its respective platform.
In order to increase manufacturing throughput for a given capital investment, two wafer platforms can be mounted in a processing chamber. However, with previously known apparatus the exact positions of the centers of the platforms can vary because of manufacturing tolerances or because of thermal expansion or contraction of the apparatus caused in turn by changes of temperature. Unless these dimensional variations are properly compensated for they can significantly affect the efficiency of edge-purging because of inaccurate centering of the wafers when placed on their respective platforms. The present invention provides a simple and effective way of overcoming these difficulties.
In accordance with the invention, in one specific aspect thereof, there is provided an apparatus for processing semiconductor wafers. The apparatus provides for accurate placement of two or more wafers onto respective processing platforms by substantially reducing mechanical tolerance and other variations in the positions of the platforms relative to that of a wafer-handling robot.
(Claim 1) From a first apparatus aspect, the present invention is an apparatus for processing multiple semiconductor wafers. The apparatus comprises a transfer chamber, first and second processing chamber, and a robot. The first processing chamber is mounted in fixed relation to the transfer chamber and has a first wafer-holding platform with a center. The second processing chamber is mounted in adjustable relation to the transfer chamber and to the master chamber and has a second wafer-holding platform with a center. The robot is rotatably mounted within the transfer chamber and has first and second wafer-holding arms spaced parallel to each other for inserting a pair of wafers simultaneously into the first and second chambers and for placing the wafers accurately centered over the respective platforms. The spacing of the platform centers is adjusted relative to the spacing of the robot arms such that the wafers are centered and placed with a preselected degree of accuracy onto the respective platforms for efficient processing of the wafers.
(Claim 3) From a second apparatus aspect, the invention is an apparatus for processing multiple semiconductor wafers. The apparatus comprises a transfer chamber, first and second processing chamber, a mechanism for adjustably mounting the second chamber in relation to the first chamber and to the transfer chamber, and a robot. The first processing chamber is mounted in known relation to the transfer chamber and has a first wafer-holding platform with a center. The second processing chamber has a second wafer-holding platform with a center. The mechanism provides a plurality of position adjustments for the second chambers. The robot is rotatably mounted within the transfer chamber and has first and second wafer-holding arms spaced parallel to each other for inserting a pair of wafers simultaneously into the first and second chambers and for placing the wafers accurately centered over the respective platforms. The spacing of the platform centers are adjusted relative to the spacing of the robot arms such that the wafers are centered and placed with a preselected degree of accuracy onto the respective platforms for efficient processing of the wafers.
(Claim 7) From a third aspect the invention is an apparatus for processing at least two semiconductor wafers simultaneously. The apparatus comprises a transfer chamber, a load-lock chamber adjacent the transfer chamber, first and second processing chambers, adjusting means for adjustably mounting the second chamber in relation to the first chamber and to the transfer chamber, and a robot. The first processing chamber is mounted in known relation to the transfer chamber and has a first wafer-holding platform with a center. The second processing chamber has a second wafer-holding platform with a center. The adjusting means has a bellows assembly positioned between the transfer chamber and the second chamber and provides for relative movement thereof and also provides a wafer passageway between the chambers while maintaining an hermetic seal. The robot is rotatably mounted around a center axis within the transfer chamber and has first and second wafer-holding arms spaced parallel to each other for withdrawing a pair of wafers from the load-lock chamber and inserting the pair of wafers simultaneously into the first and second chambers and for positioning both of the wafers with a preselected degree of accuracy over the respective platforms. The spacing of the platform centers is adjusted to a preselected degree of accuracy by the adjusting means relative to each other and to the spacing of the robot arms and the center axis such that the wafers are centered and placed with the preselected degree of accuracy onto the respective platforms for efficient processing of the wafers.
(Claim 9) From a fourth aspect the invention is an apparatus for processing a pair of semiconductor wafers simultaneously. The apparatus comprises a transfer chamber, a load-lock chamber adjacent the transfer chamber, first and second processing chambers, mechanical means for adjustably mounting the second chamber in relation to the first chamber and to the transfer chamber, mechanical means for adjustably mounting the second chamber in relation to the first chamber and to the transfer chamber, a slit valve, and a remotely controlled robot. The first processing chamber is mounted in fixed relation to the transfer chamber and has a first wafer-holding platform with a center. The second processing chamber has a second wafer-holding platform with a center. The mechanical means supports the second chamber against the load-lock chamber in cantilever fashion and has a bellows assembly positioned between the transfer chamber and the second chamber to provide for relative movement thereof and to provide a wafer passageway between the respective chambers while maintaining an hermetic seal. The remotely controlled robot is rotatably mounted around a center axis within the transfer chamber and has first and second wafer-holding arms spaced parallel to each other for withdrawing a pair of wafers from the load-lock chamber and inserting the pair of wafers simultaneously into the first and second chambers and for positioning both of the wafers to a preselected degree of accuracy over the respective platforms. The spacing of the platform centers are adjusted by the mechanical means relative to each other and to the spacing of the robot arms and the center axis such that the wafers are centered and placed with the preselected degree of accuracy onto the respective platforms for efficient processing of the wafers.
A better understanding of the invention will be gained from the following description given in conjunction with the accompanying drawings and claims.